1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor structure.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology which are scaled down to far below 100 nm generation and provide big challenges.
Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor which is connected with a storage capacitor. The access transistor comprises source/drain regions, a channel connecting the source/drain regions as well as a gate electrode controlling an electrical current flow between the source/drain regions. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms a part of a word-line and is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word-line, the information stored in the storage capacitor is read out or programmed. In particular, the information is read out to a corresponding bit-line via a bit-line contact.
In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends in the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell, the electrical charge is stored in a stacked capacitor which is formed above the surface of the substrate.
Memory devices usually comprise a memory cell array and a peripheral device area. Generally, the peripheral device area of memory devices includes circuitry for addressing memory cells and for sensing and processing the signals received from the individual memory cells. Usually, the peripheral portion is formed in the same semiconductor substrate as the individual memory cells. Hence, it is highly desirable to have a robust manufacturing process by which a cell array and peripheral components of the memory device can be formed simultaneously and safely with high yield.
U.S. Pat. No. 7,034,408 B1 the disclosure of which is fully incorporated herein by reference discloses a memory device and a method of manufacturing a memory device.
Particularly, the known method comprises the steps of: Forming memory cells by providing access transistors, each of the access transistors comprising a first and a second source/drain region, a channel disposed between the first and the second source/drain regions and a gate electrode that is electrically isolated from the channel and adapted to control the conductivity of the channel, the access transistor being at least partially formed in a semiconductor substrate including a surface, and by providing storage elements for storing information, each of the storage elements being adapted to be accessed by one of the access transistors; providing bit-lines extending in a first direction along the substrate, the bit-lines being connected to the first source/drain regions of the access transistors via bit-line contacts; providing word-lines extending in a second direction along the substrate, the second direction intersecting the first direction; and providing peripheral circuitry, the peripheral circuitry comprising at least one peripheral transistor, the peripheral transistor comprising a first and a second peripheral source/drain region, a peripheral channel connecting the first and second peripheral source/drain regions and a peripheral gate electrode controlling the conductivity of the peripheral channel, the gate electrode of the access transistor forming part of one of the word-lines, the peripheral circuitry being connected with the word-lines and the bit-lines, wherein a top surface of the word-line is disposed beneath the substrate surface, and the peripheral gate electrodes and the bit-lines including the bit-line contact are made by forming a layer stack comprising at least one layer on the substrate surface so as to cover the memory cells and the peripheral circuitry, and, subsequently patterning the layer stack so as to form the bit-lines and the peripheral gate electrodes.
It is a problem with this known method of manufacturing a memory device that certain metals used for the word-lines, such as TiN, TaN, W and similar ones, are very sensitive against high temperature process steps, particularly oxidation process steps, involving temperatures of typically 800° C. and above. Thus, the support or peripheral device gate oxidation can also unadvertendly oxidize the metal of the word-lines.
On the other hand, it is a difficult task to provide high temperature process steps in the beginning of the process sequence before the word-line metal deposition without making the process sequence making much more complex and without loosing a plurality of simultaneous process steps for memory cell array and periphery devices.